Simulating SiScape: A Parallel CMP Architecture

Chip multiprocessors (CMPs) with a small number of cores are already a reality, while large scale CMPs are just on the horizon. CMPs are a straightforward architectural choice to exploit increased number of transistors, in an era of diminishing frequency increase, increasing wire delays, and uncontrollable complexity. For large scale, general purpose, CMPs, on-chip interconnection networks are proposed and studied for core and memory communication.In this paper we prepare a simulator for an alternative architectural approach for CMPs, specialized for embedded applications, where cost, power and reliability are primary concerns. Our approach allows the on-chip memory and processors to act as part of the communication fabric, simplifying the system architecture, providing high bandwidth, and low power. We prepare a simulator for such a novel architecture utilizing the simulator Modelsim. We show how the architectural features are captured in the simulator and present in detail the components used.