DocumentCode :
235170
Title :
Development of exposed die large body to die size ratio wafer level package technology
Author :
Osenbach, J. ; Emerich, S. ; Golick, L. ; Cate, S. ; Chan, Mei-Lin ; Yoon, Sang Won ; Lin, Y.J. ; Wong, Kai-Kit
Author_Institution :
LSI Corp. (USA), Allentown, PA, USA
fYear :
2014
fDate :
27-30 May 2014
Firstpage :
952
Lastpage :
955
Abstract :
Traditionally fan out wafer level package technology has been associated with lower power, smaller body sizes (typically <; 8 mm × 8 mm), small body-to-die size area ratios (<;2) and fine pitch BGAs (0.4 mm or less). This work extends this technology to larger body sizes up to 13 mm × 13 mm, higher powers, > 5 W, and larger body-to-die size area ratios up to 10.5. It is shown that such packages can be readily manufactured in a 300 mm wafer format with yields exceeding 99% and final package warpage <; 75 um. Further, data is presented showing that 10 mm × 10 mm packages with a body to die area ratio of 6.25 are compatible with moisture sensitivity level 1, and easily pass 2000 temperature cycle (-55C to 125C air to air) and 288 hr uHAST. That is to say they have reliability that is compatible with that required for all storage and communications applications. Larger package sizes, up to 13 mm × 13 mm, and body-to-die area ratios, > 10, have also been demonstrated. However, failures in extended temperature cycle were found in these larger packages. All of the failures were due to pre-identified package design flaws that violated well established rules. This indicates if such packages were designed with no rule violations then they would meet the reliability requirements needed for communications and storage applications..
Keywords :
ball grid arrays; fine-pitch technology; reliability; wafer level packaging; body-to-die size area ratios; communications applications; die size ratio; exposed die large body; fine pitch BGA; package warpage; pre-identified package; reliability requirements; storage applications; temperature cycle; wafer format; wafer level package technology; Compounds; Electronic packaging thermal management; Electronics packaging; Materials; Reliability; Routing; Stress;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location :
Orlando, FL
Type :
conf
DOI :
10.1109/ECTC.2014.6897403
Filename :
6897403
Link To Document :
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