Title :
A new motion estimation core dedicated to H.263 video coding
Author :
Fujita, Gen ; Onoye, Takao ; Shirakawa, Isao
Author_Institution :
Dept. of Inf. Syst. Eng., Osaka Univ., Japan
Abstract :
A VLSI architecture of a motion estimator is described for the H.263 low bitrate video coding. Adopting an efficient hierarchical search algorithm, a new motion estimator yields high quality vectors with small area occupancy and at a low operation frequency. A one-dimensional Processing Element array is devised to be tuned to the H.263 encoding, which treats both the advanced prediction mode and the PB-frame mode. The proposed motion estimation core is integrated in 1.34 mm2 by using 0.35 μm CMOS 3LM technology, which operates at 15 MHz, and hence enables the realtime motion estimation of QCIF pictures
Keywords :
CMOS digital integrated circuits; VLSI; data compression; digital signal processing chips; motion estimation; prediction theory; video coding; 0.35 micron; 15 MHz; CMOS 3LM technology; H.263 video coding; PB-frame mode; VLSI architecture; advanced prediction mode; area occupancy; hierarchical search algorithm; low bitrate video coding; motion estimation core; one-dimensional processing element array; operation frequency; realtime motion estimation; Bit rate; Clustering algorithms; Computational efficiency; Computer architecture; Encoding; Frequency; Motion detection; Motion estimation; Very large scale integration; Video coding;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.622018
