Title :
Comparison of fully depleted and partially depleted mode transistors for practical high-speed, low-power 0.35 μm CMOS/SIMOX circuits
Author :
Yoshino, Akira ; Kumagai, Kouichi ; Hamatake, Nobuhisa ; Kurosawa, Susumu ; Okumura, Koichiro
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
Abstract :
Although attractive features of fully depleted mode transistors have already been clarified, essential roles of the fully depleted mode itself in improved performance of digital circuits have not been shown clearly. In this study, we examined such parameters as the propagation delay time and power consumption of 0.35-μm CMOS/SIMOX gates (inverter, 2-6NAND, 2-6NOR) composed of fully depleted (FD), near fully depleted (n-FD), or partially depleted (PD) mode transistors with no body-contacts, and discussed the essentially important factors for high performances of CMOS/SIMOX circuits
Keywords :
CMOS logic circuits; MOSFET; NAND circuits; NOR circuits; SIMOX; combinational circuits; logic gates; 0.35 micron; CMOS digital circuits; CMOS/SIMOX circuits; NAND circuits; NOR circuits; fully depleted mode transistors; inverter; partially depleted mode transistors; power consumption; propagation delay time; CMOS process; CMOS technology; Circuit testing; Energy consumption; Impurities; Inverters; National electric code; Propagation delay; Space technology; Threshold voltage;
Conference_Titel :
SOI Conference, 1994 Proceedings., 1994 IEEE International
Conference_Location :
Nantucket, MA
Print_ISBN :
0-7803-2406-4
DOI :
10.1109/SOI.1994.514269
