DocumentCode :
2352198
Title :
Different Approaches for Clock Skew Analysis in Present and Future Synchronous IC´s
Author :
Tosik, Grzegorz ; Gallego, Luis Manuel Santana ; Lisik, Zbigniew
Author_Institution :
Tech. Univ. of Lodz, Lodz
fYear :
2007
fDate :
9-12 Sept. 2007
Firstpage :
1227
Lastpage :
1232
Abstract :
One of the major performance limitations in chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Clock skew can limit overall circuit performance, or even cause functional errors. The main goal of this paper is to analyse and compare the most popular analytical models for estimating the clock skew for present and future VLSI systems. These models are compared for a generic global clock distribution network (an H-tree) with a JAVA program. Finally based on the presented models, a prevision for the clock skew value in upcoming technology nodes will be given.
Keywords :
Java; VLSI; clocks; digital integrated circuits; integrated circuit design; logic CAD; logic design; JAVA program; VLSI systems; chip design; clock skew analysis; synchronous IC; Analytical models; Circuit optimization; Circuit simulation; Clocks; Delay; Frequency synchronization; Java; System performance; Uncertainty; Very large scale integration; CDN; OCDN; OVLSI; clock skew; optical interconnects;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
EUROCON, 2007. The International Conference on "Computer as a Tool"
Conference_Location :
Warsaw
Print_ISBN :
978-1-4244-0813-9
Electronic_ISBN :
978-1-4244-0813-9
Type :
conf
DOI :
10.1109/EURCON.2007.4400541
Filename :
4400541
Link To Document :
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