Title :
Minimization of threshold voltage variation in SOI MOSFETs
Author :
Sherony, Melanie J. ; Su, Lisa T. ; Chung, James E. ; Antoniadis, Dimitri A.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
Abstract :
SOI NMOS devices incorporating the constant dose design concept were fabricated. The devices had a gate oxide of 8 nm, a buried oxide of 380 nm, and a silicon film thickness (tSi) that ranged between 42 nm to 53 nm. All measurements were taken on long channel (L eff>2 μm) devices. The devices implanted with the lowest energy of 20 keV are less sensitive to tSi variations than those with the higher implant energy conditions. For comparison, the threshold voltage (VT) calculated from the analytical model of Lim et al. (1983) is also shown for the constant substrate dopings of 3×1017 cm-3 and 4×1017 cm-3. The VT sensitivity to tSi variations was reduced considerably by using the constant dose design concept
Keywords :
MOSFET; buried layers; ion implantation; semiconductor process modelling; silicon-on-insulator; 1D process simulator; 380 nm; 42 to 53 nm; 8 nm; SOI MOSFETs; SOI NMOS devices; SUPREM-III; Si film thickness; buried oxide; constant dose design concept; constant substrate doping; gate oxide; implant energy; long channel devices; threshold voltage variation minimization; Analytical models; Doping; Implants; MOS devices; MOSFETs; Semiconductor films; Silicon; Substrates; Thickness control; Threshold voltage;
Conference_Titel :
SOI Conference, 1994 Proceedings., 1994 IEEE International
Conference_Location :
Nantucket, MA
Print_ISBN :
0-7803-2406-4
DOI :
10.1109/SOI.1994.514281
