Title :
An integrated design flow for a via-configurable gate array
Author :
Yajun Ran ; Marek-Sadowska, M.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
In This work we present a complete physical design flow for a via-configurable gate array (VCGA). The VCGA is an array of prefabricated logic blocks and fixed metal masks. The block consists of via-configurable functional cells and a via-decomposable flip-flop. An M1-M2 via mask is used to define the block´s functionality. Interconnects are customized using via masks. We developed a physical design flow for VCGA, which integrates a set of effective techniques. Here, we highlight the packing, cell-binding, and detailed-routing problems. We use our design flow to compare the VCGA-based and standard-cell/FPGA-based designs. Experimental results show the efficiency of our flow.
Keywords :
flip-flops; integrated circuit design; integrated circuit interconnections; logic design; FPGA-based design; M1-M2 via mask; VCGA-based design; fixed metal masks; integrated design flow; prefabricated logic blocks; standard-cell based design; via-configurable functional cells; via-configurable gate array; via-decomposable flip-flop; Costs; Fabrics; Field programmable gate arrays; Logic arrays; Manufacturing; Productivity; Radio access networks; Routing; Switches; Wires;
Conference_Titel :
Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-8702-3
DOI :
10.1109/ICCAD.2004.1382644
