Mechanical stress management for electrical chip-package interaction (e-CPI)

e-CPI has emerged as a new risk in modern chip design as silicon dies become increasingly thinner and packages become increasingly more complex. e-CPI is different from traditional mechanical reliability related chip-package interaction, as it focuses on package stress impact on electrical circuit performance. A complete e-CPI modeling flow has been demonstrated. Both package FEA models and silicon piezoresistance coefficients are important for evaluating e-CPI risks. A case study of a product level circuit yield loss issue due to e-CPI has been discussed and modeled. The model has successfully reproduced the failure mechanism. Circuit designers, package designers, silicon foundries and package assembly houses should all take part in managing e-CPI risks.