Title :
An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop
Author :
Sharma, Manoj ; Noor ; Tiwari, Shatish Chandra ; Singh, Kunwar
Author_Institution :
SoE, C-DAC, Noida, India
Abstract :
In this paper, a single edge-triggered, static D flip-flop design suitable, for low power and low area requirements is proposed. Advantageously, the flip-flop is realized using only ten transistors. The flip-flop is implemented using master-slave configuration and can be used for lower cost memory and microprocessor chips. The 0.6-micron technology is used to implement the design and the area and power results were compared with existing SET D FFs. Simulation results indicated that the circuit is capable of significant power savings.
Keywords :
flip-flops; high-speed integrated circuits; logic design; logic simulation; low-power electronics; high-speed applications; low power circuit; master-slave configuration; power efficient design; power savings; single edge triggered static D-flip flop; size 0.6 micron; Capacitance; Circuits; Clocks; Communications technology; Delay; Feedback loop; Flip-flops; Latches; Logic; Master-slave; D flip flip; SETDFF;
Conference_Titel :
Advances in Recent Technologies in Communication and Computing, 2009. ARTCom '09. International Conference on
Conference_Location :
Kottayam, Kerala
Print_ISBN :
978-1-4244-5104-3
Electronic_ISBN :
978-0-7695-3845-7
DOI :
10.1109/ARTCom.2009.207
