DocumentCode
2352604
Title
FSR-a fair switching architecture
Author
Pyssysalo, Tino ; Raatikainen, Pertti ; Zidbeck, Juha
Author_Institution
Digital Syst. Lab., Helsinki Univ. of Technol., Espoo, Finland
fYear
1995
fDate
14-16 Jun 1995
Firstpage
116
Lastpage
123
Abstract
The paper introduces a high speed interconnection network, the Frame Synchronized Ring (FSR), for use in broadband switching applications. The structure as well as the performance of the switching architecture are described and followed by deadlock and fairness analysis. Fair and deadlock free performance is analysed and proved by a predicate/transition net analysis tool, PROD. Finally, an example construction of an FSR based ATM switch is presented including some performance figures. Another example presents the FSR as a real time video switch, that switches and multiplexes several digitized video signals simultaneously with other high bit rate data connections
Keywords
asynchronous transfer mode; broadband networks; concurrency control; multiprocessor interconnection networks; synchronisation; video signal processing; FSR; FSR based ATM switch; Frame Synchronized Ring; PROD; broadband switching applications; deadlock free performance; digitized video signals; fair switching architecture; fairness analysis; high bit rate data connections; high speed interconnection network; predicate/transition net analysis tool; real time video switch; Broadband communication; Communication switching; Computer architecture; Digital systems; Media Access Protocol; Network topology; Performance analysis; Switches; Synchronization; System recovery;
fLanguage
English
Publisher
ieee
Conference_Titel
Real-Time Systems, 1995. Proceedings., Seventh Euromicro Workshop on
Conference_Location
Odense
ISSN
1068-3070
Print_ISBN
0-8186-7112-2
Type
conf
DOI
10.1109/EMWRTS.1995.514301
Filename
514301
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