DocumentCode :
2352661
Title :
Failure modes & effects analysis (FMEA) of flip chip devices attached to printed wiring boards (PWB)
Author :
Kennedy, Melinda
Author_Institution :
Medtronic Micro-Rel, Tempe, AZ, USA
fYear :
1998
fDate :
19-21 Oct 1998
Firstpage :
232
Lastpage :
239
Abstract :
Assembly techniques using flip chip devices on PWB and ceramic have been available for several years. When Medtronic Micro-Rel decided to introduce this technology or change some of the design, component, or process parameters, failure modes and effects analysis (FMEA) proved to be a useful tool to identify any potential design and process related failure modes. Additional purposes of an FMEA are: to determine the effects of the failure modes; to determine the root cause of the failure modes; to prioritize actions using a ranking system for failure mode effects in terms of failure mode occurrence probability, failure mode effect severity and failure mode detection probability through manufacturing; to identify, implement, and document corrective actions to address failure modes with rankings that are considered unacceptable. The purpose of this paper is to address FMEA by dividing the process into smaller pieces for manageability. Also, this report addresses preliminary FMEA performed early in the evaluation stage of flip chip devices on PWB. Many initial inputs were based on available literature, and many of the evaluations and designed experiments (DOE) performed were driven by the initial FMEA rankings. During development, six DOEs were recorded and performed, addressing various issues related to flip chip attachment. Areas reviewed included solder screening, reflow profiles of the flip chip dice, and underfill dispense parameters. The FMEA was then reevaluated after all evaluations and qualification builds were performed. These findings were used to drive design rules and process parameters
Keywords :
chip-on-board packaging; design of experiments; encapsulation; failure analysis; flip-chip devices; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; microassembling; printed circuits; probability; reflow soldering; FMEA; FMEA rankings; PWB; assembly techniques; ceramic substrates; corrective actions; design related failure modes; design rules; designed experiments; failure mode detection probability; failure mode effect severity; failure mode effects; failure mode occurrence probability; failure mode rankings; failure mode root cause; failure modes; failure modes and effects analysis; flip chip attachment; flip chip device attach; flip chip devices; flip chip dice; flip chip on PWB; printed wiring boards; process parameters; process related failure modes; qualification builds; ranking system; reflow profiles; solder screening; underfill dispense parameters; Assembly; Ceramics; Failure analysis; Flip chip; Manufacturing; Performance evaluation; Printing; Process design; Pulp manufacturing; Qualifications; Reliability engineering; Risk analysis; Surface cleaning; US Department of Energy; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Manufacturing Technology Symposium, 1998. Twenty-Third IEEE/CPMT
Conference_Location :
Austin, TX
ISSN :
1089-8190
Print_ISBN :
0-7803-4523-1
Type :
conf
DOI :
10.1109/IEMT.1998.731080
Filename :
731080
Link To Document :
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