DocumentCode
2352823
Title
Design of self-parity combinational circuits for self-testing and on-line detection
Author
Sogomonjan, E.S. ; Goessel, M.
Author_Institution
Inst. of Control, Acad. of Sci., Moscow, Russia
fYear
1993
fDate
27-29 Oct 1993
Firstpage
239
Lastpage
246
Abstract
It is shown that an arbitrary n-tupel of M-ary Boolean functions can be systematically implemented as a self-testing combinational circuit. This is achieved by the use of a parity bit and of one or more replicates of a selected part of the monitored circuit. The party bit and the functional bits are thus jointly designed rather than in separation. The circuit is then called a self-parity circuit. In comparison to a separate implementation of a parity prediction function, the hardware costs can be significantly reduced. The circuit can be used in test mode and in normal operation mode for online fault detection. In normal online operation, faults may be detected with some degree of latency
Keywords
combinational circuits; M-ary Boolean functions; circuit graph; fault model; on-line detection; parity bit; parity prediction; partial node splitting; self-parity combinational circuits; self-testing; Boolean functions; Built-in self-test; Circuit faults; Circuit testing; Combinational circuits; Cost function; Electrical fault detection; Fault detection; Hardware; Monitoring;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on
Conference_Location
Venice
ISSN
1550-5774
Print_ISBN
0-8186-3502-9
Type
conf
DOI
10.1109/DFTVS.1993.595814
Filename
595814
Link To Document