Design of RF and thermal pads of CMOS PAs using copper to copper bonding technology

Different radios require different levels of power output; for example, GSM demands up to 4 W (36 dBm) for its RF operations. CMOS RFICs are frequently designed up to 2 W (32+ dBm) [1, 2]. Recently, copper to copper bonding technology has been fiercely pursued in C2W and W2W domains [3-5]. However, the technology is equally applicable in other packaging platforms where similar materials are packaged; for example, CMOS PAs (Power Amplifiers) being integrated onto other silicon platforms, such as Si-IPD and Silicon interposer. It is because the high stress occurred at the low profiled copper to copper bonding interface can be avoided (or properly managed) when the thermal expansion coefficients of the two materials are the same or similar. Here we study the RF and thermal pad designs for CMOS PA packaged onto Si-IPD or Si-interposer using copper to copper bonding. The results will be compared to those using flip chip bumps. For RF I/O pad design, G-S I/O configuration is assumed. The frequency band of interest is up to 60 GHz. For thermal design, the PA die sizes vary from 0.7 mm × 0.7 mm to 2 mm × 2 mm. Thermal pad sizes are 50 μm × 50 μm and 75 μm × 75 μm. We assumed two isolated heating sources; each heating source outputs 1 W (total 2W, 33 dBm). Using Cadence´s thermal design tools, steady state and transient results were obtained for Cu-Cu bonding. Results for flip chip bump technologies were then extrapolated from the Cu-Cu bonding results. The junction temperature difference between the systems employing these two technologies was significant; using Cu-Cu bonding technique, the junction temperature of PA can be significantly lower (about 50 °C) than 110 °C, the simulated junction temperature of the PA system employing flip chip technology. This represents a huge benefit on the reliability of device using Cu-Cu bonding technology.