ABACUS: A novel array multiplier-accumulator architecture for low energy applications

Design and verification of a novel array multiplier-accumulator architecture, named ABACUS, is introduced in this paper. The design priority in this architecture is low energy operation instead of the traditional `performance-first´ approach. ABACUS uses a threshold function to implement multiple fast carry operations in parallel through a cellular array, and therefore significantly deviates from the conventional approaches based on half/full adder or counter building blocks. The ABACUS architecture was formally verified for correct functionality of any unsigned m × n multiplication. Hardware implementation has been validated on FPGAs. The energy-delay advantages were architecturally analyzed over the traditional carry-save array, and circuit implementation focus areas have been accordingly developed.