Effects of epitaxial silicon technology on the manufacturing performance of wafer fabrication lines [isolation]

This paper evaluates the manufacturing benefits of silicon selective epitaxial growth (SEG) as a front-end device isolation fabrication process. The technology is evaluated in two different ways. First, the cost of ownership (COO) of the equipment is used to obtain a cost of process (COP) for SEG and compared to the current alternatives, which are local oxidation of silicon (LOCOS) and shallow trench isolation (STI). Results of the processes, up to the point where the CMOS MOSFETs are produced, show that cost reductions using SEG was more than 22% compared to LOCOS and 49% compared to STI. The second evaluation approach examines the effects of the three processes on the mean and variance of fabrication cycle time using queuing network models. These results indicate that the mean cycle time for the portion of the line being considered could drop by as much as one third when the dielectric isolation by SEG (DI-SEG) process is implemented. Significant increases in line yield may also result