Title :
Effects of epitaxial silicon technology on the manufacturing performance of wafer fabrication lines [isolation]
Author :
Hughes, John C. ; Neudeck, Gerold W. ; Uzsoy, Reha
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
This paper evaluates the manufacturing benefits of silicon selective epitaxial growth (SEG) as a front-end device isolation fabrication process. The technology is evaluated in two different ways. First, the cost of ownership (COO) of the equipment is used to obtain a cost of process (COP) for SEG and compared to the current alternatives, which are local oxidation of silicon (LOCOS) and shallow trench isolation (STI). Results of the processes, up to the point where the CMOS MOSFETs are produced, show that cost reductions using SEG was more than 22% compared to LOCOS and 49% compared to STI. The second evaluation approach examines the effects of the three processes on the mean and variance of fabrication cycle time using queuing network models. These results indicate that the mean cycle time for the portion of the line being considered could drop by as much as one third when the dielectric isolation by SEG (DI-SEG) process is implemented. Significant increases in line yield may also result
Keywords :
CMOS integrated circuits; MOSFET; cost-benefit analysis; elemental semiconductors; epitaxial growth; integrated circuit testing; integrated circuit yield; isolation technology; semiconductor process modelling; silicon; CMOS MOSFETs; LOCOS process; STI process; Si; SiO2-Si; cost of ownership; cost of process; cost reduction; dielectric isolation; dielectric isolation-SEG process; epitaxial silicon technology; fabrication cycle time mean; fabrication cycle time variance; front-end device isolation fabrication process; line yield; local oxidation of silicon; manufacturing performance; mean cycle time; queuing network models; shallow trench isolation; silicon SEG; silicon selective epitaxial growth; wafer fabrication lines; CMOS process; Costs; Epitaxial growth; Fabrication; Isolation technology; MOSFETs; Manufacturing processes; Oxidation; Pulp manufacturing; Silicon;
Conference_Titel :
Electronics Manufacturing Technology Symposium, 1998. Twenty-Third IEEE/CPMT
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-4523-1
DOI :
10.1109/IEMT.1998.731090
