Cost and performance effective silicon interposer and Vertical Interconnect for 3D ASIC and memory integration

To enable three-dimensional (3D) ASIC and memory integration, large-size silicon interposer is a critical technology [1]. Currently most silicon interposers are manufactured by wafer foundries and are limited in size by the wafer lithographic processing. In this study, manufacturing of cost- and performance-effective, large-size silicon interposers are investigated. The existing supply chain and infrastructure of high-performance flip-chip packaging substrates is leveraged. A 3D System-in-Package (SiP) is designed and manufactured that includes a large-size silicon interposer with Through-Silicon-Vias (TSV) and Cu wiring layers on both sides of the silicon interposer. To develop the assembly process for the 3D SiP, thermal deformation of each constituent component is analyzed using metrological techniques such as Digital Image Correlation (DIC). With the assembly process developed, an ASIC die is attached on top of the silicon interposer while two smaller memory dice are attached to the bottom of the silicon interposer with micro-bump interconnection. The 3D IC stack is then assembled on an organic package substrate with two Vertical Interconnect Spacers (VISs) and “regular” solder bumps so the bottom dice can be accommodated without any interference to the planar organic substrate. The completed 3D SiP module is finally assembled on a test board using a lead-free surface mount process. Thermo-mechanical reliability of the 3D SiP assembly is studied using temperature cycling testing. Both the thermal deformation analysis and stress testing results are used to gain insights into the 3D IC technology and to enable ASIC and memory integration for next generation high-performance network systems.