CMOS hot carrier lifetime improvement from deuterium anneal

Author

Li, E. ; Rosenbaum, E. ; Tao, J. ; Fang, P.

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

fYear

1998

fDate

22-24 June 1998

Firstpage

22

Lastpage

23

Abstract

It has been demonstrated that post-metallization anneal in a deuterium ambient increases the hot carrier lifetime of NMOS devices biased at the peak substrate current (Lyding et al, 1996; Kizilyalli et al., 1997). In this work, for the first time, we report on the lifetime improvement factor for both NMOS and PMOS devices stressed at a variety of DC and AC bias conditions. The devices studied were fabricated using an advanced 0.25 μm dual-poly gate CMOS technology with 4 nm gate oxide thickness.

Keywords

CMOS integrated circuits; annealing; carrier lifetime; deuterium; hot carriers; integrated circuit metallisation; integrated circuit testing; 0.25 micron; 4 nm; AC bias conditions; CMOS hot carrier lifetime; D; DC bias conditions; NMOS devices; PMOS devices; Si; SiO/sub 2/-Si; deuterium ambient; deuterium anneal; dual-poly gate CMOS technology; gate oxide thickness; hot carrier lifetime; lifetime improvement factor; peak substrate current bias; post-metallization anneal; Annealing; Deuterium; Hot carriers;

fLanguage

English

Publisher

ieee

Conference_Titel

Device Research Conference Digest, 1998. 56th Annual

Conference_Location

Charlottesville, VA, USA

Print_ISBN

0-7803-4995-4

Type

conf

DOI

10.1109/DRC.1998.731105

Filename

731105