DocumentCode
2353285
Title
FPGA hardware of the LSB steganography method
Author
Mohd, Bassam Jamil ; Abed, Saed ; Al-Hayajneh, Thaier ; Alouneh, Sahel
Author_Institution
Comput. Eng. Dept., Hashemite Univ., Zarqa, Jordan
fYear
2012
fDate
14-16 May 2012
Firstpage
1
Lastpage
4
Abstract
Steganography is one of the most powerful techniques to conceal the existence of hidden secret data inside a cover object. Images are the most popular cover objects for steganography, and thus the importance of image steganography. Embedding secret information inside images requires intensive computations, and therefore, designing steganography in hardware speeds up steganography. This work presents a hardware design of Least Significant Bit (LSB) steganography technique in a cyclone II FPGA of the Altera family. The design utilizes the Nios embedded processor as well as specialized logic to perform the steganography steps. The design balances the tradeoffs such as imperceptibility, quality and capacity.
Keywords
data privacy; embedded systems; field programmable gate arrays; image coding; steganography; Altera family; FPGA hardware; LSB steganography method; Nios embedded processor; cover object; cyclone II FPGA; embedded secret information; hidden secret data; image steganography; least significant bit steganography technique; Bit error rate; Educational institutions; Field programmable gate arrays; Hardware; Measurement; PSNR; SDRAM; FPGA; Security; Steganography;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer, Information and Telecommunication Systems (CITS), 2012 International Conference on
Conference_Location
Amman
Print_ISBN
978-1-4673-1549-4
Type
conf
DOI
10.1109/CITS.2012.6220393
Filename
6220393
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