Fine-grain data threaded in-order architecture

This paper describes a novel 2-wide in-order simultaneous multithreading core architecture that performs fine-grain data-dependence based threaded execution in hardware, when there is only one available software thread. Performance simulation on a subset of Spec 2000 benchmarks shows our architecture gives 7% average reduction in single-thread execution time compared to the same core without the enhancement. The enhanced SMT architecture uses about the same hardware, and thus consumes about the same power.