Formal derivation of optimal active shielding for low-power on-chip buses

Passive shielding has been used to reduce capacitive coupling effects of adjacent bus lines by inserting passive ground or power lines (shields) between the bus lines. Active shielding is another shielding technique, in which the shield is allowed to switch depending on the switching pattern of its adjacent bus lines. This work formally derives the optimal active shielding logic function for minimum power dissipation. It is also shown that this optimal active shielding architecture depends on the ratio of coupling to ground capacitance (γ = C_c/C_g). Optimal active shielding is shown to provide up to 25% reduction in bus power dissipation compared to conventional passive shielding. A sub-optimal active shielding architecture with simpler hardware is also proposed. Simulation results show that using the sub-optimal shielding architecture leads to less than 6% bus power penalty compared to the optimal active shielding logic circuit.