Title :
Design and implementation of a merged on-line and off-line self-testable architecture
Author :
Sun, X. ; Serra, M.
Author_Institution :
Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
Abstract :
The authors present a new testing scheme which merges concurrent checking and off-line BIST, sharing resources. A simple design template is described, together with an evaluation of area, fault coverage and latency
Keywords :
built-in self test; concurrent checking; fault coverage; latency; merged design; off-line BIST; online/offline testing merge; self-testable architecture; signature analysis; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Computer architecture; Cyclic redundancy check; Delay; Hardware; Sun; System testing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on
Conference_Location :
Venice
Print_ISBN :
0-8186-3502-9
DOI :
10.1109/DFTVS.1993.595817
