Complete tests in algorithm-based fault-tolerant matrix operation on processor arrays

Author

Wei, Dah-Yea D. ; Kim, Jung H. ; Rao, T.R.N.

Author_Institution

Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA

fYear

1993

fDate

27-29 Oct 1993

Firstpage

255

Lastpage

262

Abstract

Recently, F. T. Assaad and S. Dutt (1992) proposed the hybrid checksum test method for the floating-point matrix-matrix multiplication in ABFT environment, by which the error coverage can be greatly increased. However, the thresholded test in their approach is still not avoidable in the floating-point additions involved in matrix multiplication and the number of error detections decrease with the increase in the dynamic range of data, which is not totally satisfactory. The authors present an effective method, called concurrent floating-point checksum (CFPC) test, which provides very convincing error detection/correction capabilities for the part of floating-point addition with a minimum time latency and hardware overhead

Keywords

fault tolerant computing; concurrent floating-point checksum; error correction; error detections; fault-tolerant matrix; floating-point additions; floating-point matrix-matrix multiplication; hardware overhead; hybrid checksum test; minimum time latency; processor arrays; thresholded test; Computer errors; Delay; Dynamic range; Encoding; Error correction; Fault detection; Fault tolerance; Hardware; Performance evaluation; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on

Conference_Location

Venice

ISSN

1550-5774

Print_ISBN

0-8186-3502-9

Type

conf

DOI

10.1109/DFTVS.1993.595819

Filename

595819