High I/O plastic ball grid array packages-AT&T Microelectronics experience

AT&T Microelectronics package requirements for complex high-performance 0.5 μm ASIC devices are currently in the 225 to 640 I/O range, 60 to 150 MHz, and 2 to 10 watt power dissipation. These requirements can be met with the traditional multilayer Ceramic Pin Grid Array (CPGA) packages or the lower Cost Plastic Pin Grid Array (PPGA). However, the ceramic and plastic PGAs are unwieldy and expensive at high I/O counts. Furthermore, through-hole packages are undesirable for customers who have switched to complete surface mount assembly lines. The plastic ball grid array (BGA) is a solution for lower cost, high I/O, high performance, surface mount and small outline package requirements. Using our extensive experience with plastic PGAs, we have extended the BGA technology to meet higher I/O and performance requirements. During the past two years we designed, developed and fabricated 235-388 I/O, four layer BGA packages. A 1995 production ramp up is under way. For improved electrical performance, vias were positioned to minimize trace lengths. Thermal performance was enhanced by the placement of thermal vias under the chip and direct connections to the ground plane. We have pursued two parallel BGA manufacturing paths with two different technologies: (a) overmolded BGAs through subcontract assembly; (b) Cavity type, liquid epoxy encapsulated for in-house assembly capability. Both types of BGA structures meet AT&T- ME´s device qualification requirements and can be used to ship product. We are currently developing high performance 560 and 640 BGAs in a cavity down configuration. The packages will have power and ground planes and the chip will be directly attached to a heat spreading Cu slug. We are planning to offer the high performance BGAs in the 1996 time frame