A vertical MOSFET with a leveling, surrounding gate fabricated on a nanoscale island

Several kinds of vertical MOSFET with an upward channel have been proposed and demonstrated by different authors. However, the benefit gained in terms of chip area saving is limited because micron size islands are used for the channels in all of these situations. In this paper, we present a novel vertical MOSFET with several new structural features. These features can lead to significant chip area saving (typically a reduction to one quarter) and performance improvement (due to better gate control and convenient channel engineering). They include: (1) a vertical island with nanoscale thickness; (2) superimposed source and drain; (3) a leveling and surrounding gate; (4) a withdrawn S-B junction, which can lead to a near zero junction depth; and (5) a natural connection from the channel to the substrate, which can used advantageously for the realization of a dynamic threshold and for the elimination of floating-body effects.