DocumentCode
2353706
Title
A probabilistic measurement for totally self-checking circuits
Author
Lo, Jien-Chung ; Fujiwara, Eiji
Author_Institution
Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA
fYear
1993
fDate
27-29 Oct 1993
Firstpage
263
Lastpage
270
Abstract
The authors propose a probabilistic measurement for totally self-checking (TSC) circuits. This measurement is analogous to reliability of fault-tolerant systems and is defined as the probability of achieving TSC goal (PATG). PATG surpasses the TSC definitions in determining the applicability of a circuit in a given application environment. For example, it is shown that an embedded TSC two-rail checker with two out of its four code word inputs unavailable gains a higher PATG than that in the ideal case. It is also demonstrated that the extension of PATG concept to strongly fault-secure (SFS) circuits and strongly code disjoint (SCD) checkers. The PATG can be used in product specification, analogous to reliability, and can give precise behavioral description on fault/error handling performance of TSC circuits. This is a crucial step toward the practical applications of TSC or CED circuits
Keywords
probability; embedded TSC two-rail checker; fault/error handling performance; gate level fault model; layout level fault model; probabilistic measurement; product specification; reliability; strongly code disjoint checkers; strongly fault secure circuits; switch level fault model; totally self-checking circuits; Bridge circuits; Built-in self-test; Circuit faults; Computer science; Fault tolerance; Fault tolerant systems; Physical layer; Random variables; Uncertainty; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on
Conference_Location
Venice
ISSN
1550-5774
Print_ISBN
0-8186-3502-9
Type
conf
DOI
10.1109/DFTVS.1993.595821
Filename
595821
Link To Document