High-voltage accumulation-layer UMOSFETs in 4H-SiC

During the past year, the performance of SiC power MOSFETs exceeded the theoretical limits of silicon devices for the first time. This milestone was achieved by the introduction of the first SiC accumulation-layer UMOSFET (U-ACCUFET) in 1997. In this device, an accumulation-layer channel is formed under the MOS diode by an n-type epitaxial layer on the sidewalls of the UMOS trench. The high electron mobility in the accumulation channel reduced the specific on-resistance to 10.9 mΩ-cm/sup 2/, the lowest value yet reported for a SiC power MOSFET. Although the blocking voltage of the device is only 450 V, the figure-of-merit V/sub B//sup 2//R/sub ON/ is 18.6 MW/cm/sup 2/, the highest value reported at that time for a SiC power MOSFET and about 4× higher than the theoretical limit for silicon MOSFETs. In this paper, we report an improved UMOS ACCUFET incorporating structural innovations that increase the blocking voltage to 850 V while maintaining a low on-resistance of 27 mΩ-cm/sup 2/. The resulting V/sub B//sup 2//R/sub ON/ is 26.8 MW/cm/sup 2/, about 6× higher than the theoretical limit for silicon.