Title :
Bottom-side wave solder process compatibility for 14 and 16-pin gull wing SOICs
Author :
Yang, C.M. ; Shook, R.L.
Author_Institution :
AT&T Bell Labs., Whippany, NJ, USA
Abstract :
Results are summarized on the process compatibility for bottom-side wave soldering of eleven different 14 and 16-pin plastic encapsulated Small Outline Integrated Circuits (SOICs) in a Gull Wing foot print (SOGs). Devices were preconditioned to a saturated moisture exposure of 85°C/85%RH for 168 hours (to simulate a worst case storage environment equivalent to 30°C/90%RH) before exposure to a total molten solder immersion at 260°C. A low solids flux and a terpene hydrocarbon cleaning were applied for process chemical exposure. Damage analysis was assessed through the use of C-mode Scanning Acoustic Microscopy (C-SAM) followed by Temperature-Humidity-Bias (THB) life testing. The results of these test procedures showed that nine out of eleven device codes successfully passed the wave-solder process compatibility testing. Two codes did not pass all criteria established for the process compatability. One of these codes was found to fail because of internal cracking of the mold compound. Cracks were found to originate at the top of the die and propagated laterally towards the edge of the packages. A Finite Element Model was developed for predicting internal stresses that developed during the solder immersion process. Finite Element analysis indicated that the cracking behavior is associated with the development of high stresses at the die edge as a result of a large distributed water-vapor pressure built up in die surface delaminations. Based on the experimental results and the Finite Element Analysis, it is concluded that the observed moisture induced cracking is a function of both the size of the paddle as well as the die. For those devices included in this study it is considered that wave-solder process compatibility for non-dry bagged 14 and 16 pin SOGs can be assured provided a maximum allowable paddle-to-package size is maintained
Keywords :
environmental degradation; finite element analysis; integrated circuit packaging; plastic packaging; surface mount technology; wave soldering; C-mode scanning acoustic microscopy; Small Outline Integrated Circuits; bottom-side wave soldering; chemical exposure; cracking; die surface delamination; finite element model; gull wing SOICs; internal stresses; moisture exposure; mold compound; paddle-to-package size; plastic encapsulation; process compatibility; storage environment; temperature-humidity-bias life testing; Acoustic testing; Circuit simulation; Cleaning; Finite element methods; Foot; Hydrocarbons; Moisture; Plastics; Soldering; Solids;
Conference_Titel :
Electronic Components and Technology Conference, 1995. Proceedings., 45th
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7803-2736-5
DOI :
10.1109/ECTC.1995.514364