Title :
A new self-align gated diamond field emitter array with sub-V turn-on voltage and high emission current
Author :
Wisitsora-at, A. ; Kang, W.P. ; Davidson, J.L. ; Li, Q. ; Xu, J.F. ; Kerns, D.V.
Author_Institution :
Dept. of Electr. & Comput. Sci., Vanderbilt Univ., Nashville, TN, USA
Abstract :
A new self-align gated diamond field emitter array with sub-V turn-on voltage and high emission current is reported for the first time. The new self-align gated diamond emitter array is fabricated by a new technique called "self-align-gate-molding". First, a silicon mold of inverted tips was fabricated on a p-type <100> silicon wafer via thermal oxidation, photolithographic patterning and anisotropic etching of silicon. A 0.7 μm high quality silicon dioxide layer gate dielectric was then grown on the Si inverted pyramidal mold using a dry thermal oxidation process, which at the same time produces a well-sharpened apex inverted pyramidal SiO/sub 2/ layer. Next, diamond was deposited by PECVD on the SiO/sub 2/ inverted sharpened pyramidal mold. A square window was then opened on the backside of the silicon mold and the silicon was then anisotropically etched until the SiO/sub 2/-covered diamond pyramidal apexes are exposed. Finally, the SiO/sub 2/ near the apex region was etched away to expose the sharpened diamond tips. The remaining SiO/sub 2/ and silicon form the gate dielectric and the gate (anode) respectively. The new self-align fabrication technique is simpler than the conventional self-align technique because fewer steps are used. Unnecessary deposition and etching steps of the conventional self-align process are removed. This results in a more uniform self-align gated structure with a sharper diamond tip apex and a more economical fabrication process.
Keywords :
diamond; elemental semiconductors; etching; moulding; oxidation; photolithography; plasma CVD; vacuum microelectronics; 0.7 micron; C-SiO/sub 2/-Si; Si; Si gate anode; Si inverted pyramidal mold; SiO/sub 2/ apex region etch; SiO/sub 2/ gate dielectric; SiO/sub 2/ inverted sharpened pyramidal mold; SiO/sub 2/-covered diamond pyramidal apexes; anisotropic etch; anisotropic etching; diamond PECVD; diamond tip apex; dry thermal oxidation; economical fabrication process; emission current; p-type <100> silicon wafer; photolithographic patterning; self-align fabrication technique; self-align gated diamond field emitter array; self-align-gate-molding; sharpened apex inverted pyramidal SiO/sub 2/ layer; sharpened diamond tips; silicon dioxide layer gate dielectric; silicon inverted tip mold; silicon mold backside window; square window; thermal oxidation; turn-on voltage; uniform self-align gated structure; Field emitter arrays; Voltage;
Conference_Titel :
Device Research Conference Digest, 1998. 56th Annual
Conference_Location :
Charlottesville, VA, USA
Print_ISBN :
0-7803-4995-4
DOI :
10.1109/DRC.1998.731147