Pathfinding methodology for optimal design and integration of 2.5D/3D interconnects

Given the cost per transistor is to grow below 22nm node, SOC partitioning is emerging as a viable solution compared to a monolithic solution. Ubiquitous 2.5D/3D heterogeneous integration is evolving as an eminent approach to achieve lower cost, higher bandwidth, smaller footprint and lower power. System partitioning schemes and heterogeneous integration mechanisms directly impacts performance, cost and time to market. Partitioning a single die into multiple partitions for further heterogeneous integration requires an ultra-dense connectivity. One of the key challenges in designing a low cost and high performance 2.5D/3D package is the system-level ultra-dense connectivity exploration and pathfinding. Planning an I/O ring structure and defining I/O buffer cell placement for multiple logic partitions at the early stages of 2.5D/3D product development is not trivial. Moreover, end-to-end optimization of inter-partition´s I/O cell placement, Cu pillar bump matrix and package BGA interfaced with numerous components on the PCB with fixed ball patterns is a daunting task. In this communication, we present a pathfinding methodology for the design and optimization of 2.5D/3D interconnects. We demonstrate our methodology in a 2.5D/3D design where inter-partition´s I/O buffer cells placement, Cu pillar bump matrix and package BGA are optimized in a hierarchical fashion with respect to the Wide I/O memory´s fixed bump pattern interfaced with the PCB level components placement and connectivity. We further demonstrate the cross domain flexibility and robustness of our methodology by performing an end-to-end pathfinding on ultra-dense 2.5D/3D silicon interposer and single SOC device interfaced with fixed components on a PCB.