DocumentCode
2354411
Title
Cost analysis: solder bumped flip chip versus wire bonding
Author
Lau, John ; Chen, Ray
Author_Institution
Express Packaging Syst. Inc., Palo Alto, CA, USA
fYear
1998
fDate
19-21 Oct 1998
Firstpage
464
Lastpage
472
Abstract
The cost of wire bonding chip and solder bumped flip chip on board or on organic substrate is studied. The effects of IC chip yields, gold and solder materials, and the major equipment of these technologies on costs are examined. Useful equations and charts for determining the cost of and comparing the cost between these technologies are provided
Keywords
chip-on-board packaging; costing; flip-chip devices; integrated circuit bonding; integrated circuit packaging; integrated circuit yield; lead bonding; microassembling; soldering; Au; IC chip yields; chip wire bonding; cost analysis; cost comparison; cost determination; equipment costs; gold wires; organic substrate; solder bumped flip chip; solder bumped flip chip on board; solder materials; wire bonding; Bonding; Costs; Electronic equipment testing; Encapsulation; Equations; Flip chip; Gold; Integrated circuit interconnections; Packaging; Substrates; System testing; Wafer bonding; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Manufacturing Technology Symposium, 1998. Twenty-Third IEEE/CPMT
Conference_Location
Austin, TX
ISSN
1089-8190
Print_ISBN
0-7803-4523-1
Type
conf
DOI
10.1109/IEMT.1998.731173
Filename
731173
Link To Document