Wafer level warpage characterization for backside manufacturing processes of TSV interposers

TSV (through-silicon-via) has been regarded as a key technology for 2.5D and 3D electronic packaging. However, the manufacturing of the through silicon interposer (TSI) is very challenging and costly. The minimization of the warpage of the TSV interposer wafer is crucial for successful subsequent processing, for example, thin wafer handling, backside via revealing and copper pillar bumping. In this paper, warpage was tested before and after most of the backside process steps. Wafer level warpage modeling methodology has been developed by finite element analysis (FEA) using equivalent material model. The warpage was simulated and analyzed by considering different process factors.