Low-cost manufacturing strategy for miniature packaging

The common view is that as packages decrease in size, as with chip scale packages (CSPs), the cost becomes a major impediment to implementation for high volume production. However, cost is only one aspect. In some cases, even though the cost is higher than standard equivalent surface mount packages, CSPs are still used due to the benefits obtained from miniaturization. Furthermore, current market trends show that CSP costs are falling rapidly, at least with the high volume memory products. In the longer term, the adoption of CSPs will match with the ability of the PCB infrastructure to supply cost-effective substrates. This paper discusses a manufacturing approach for CSPs to produce lower overall cost-of-ownership. The strategy centers on an organic substrate-based CSP that simplifies the back end manufacturing flow, from chip attach to wire bonding to molding through testing and singulation. Devices are attached to the strip-like substrate with designs routed out into a matrix format. This design allows the various assembly operations to be performed on existing equipment tailored previously for leadframe-based packages rather than with dedicated (and expensive) tools. Hence, more flexibility can be obtained from the assembly facilities, which are already equipped with standard equipment, boosting at the same time the machines utilization efficiency. The concept has been demonstrated for 8-lead devices and below. It has been extended to 16-, 20-, 24-, 28-, 48-, 64-, and 100-lead devices, with higher pin counts under development