Title :
CAD flows for chip-package codesign
Author :
Varma, Hbrish ; Glaser, Alan ; Franzon, Paul
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Abstract :
A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package codesign.
Keywords :
circuit layout CAD; flip-chip devices; integrated circuit layout; integrated circuit packaging; multichip modules; CAD flows; Cadence package; automatic extraction; chip-package codesign; commercial design environment; connectivity design; design rule checking; design time; flip-chip multichip module; integrated circuit design; layout design; physical design; unified method; Delay; Design automation; Integrated circuit packaging; Integrated circuit synthesis; Multichip modules; Radio frequency; Radiofrequency identification; Routing; Timing; User interfaces;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2003
Conference_Location :
Princeton, NJ, USA
Print_ISBN :
0-7803-8128-9
DOI :
10.1109/EPEP.2003.1249989
