A simultaneous switching noise design algorithm for leadframe packages with or without ground plane

Author

Huang, Chender ; Yang, Yaochao ; Prince, John L.

Author_Institution

Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA

fYear

1995

fDate

21-24 May 1995

Firstpage

351

Lastpage

360

Abstract

This paper provides design techniques for leadframe packages with or without a ground plane, which enable an accurate estimate of the maximum Simultaneous Switching Noise (SSN) and the required numbers of power and/or ground pins for pre-specified SSN limits early in the design phase. Two heuristic design approaches, namely equal-angle and quarter-plane, are proposed as initial design choices for the lead frame design to meet pre-specified SSN constraint. Effects of the signal conductors in reducing the effective inductance of a leadframe package are quantified. Closed-form equations and SPICE simulation are used to calculate the Simultaneous Switching Noise. A design example for a 28×28 mm Plastic Quad Flat Package (PQFP) is given to provide guidelines for SSN-constrained design. The design algorithm is integrated into a CAD tool, UASSNS3.0, which is capable of initial SSN design of leadframe packages

Keywords

SPICE; integrated circuit design; integrated circuit noise; integrated circuit packaging; SPICE simulation; UASSNS3.0 CAD tool; design algorithm; equal-angle design; ground plane; inductance; leadframe package; plastic quad flat package; quarter-plane design; signal conductors; simultaneous switching noise; Algorithm design and analysis; Conductors; Equations; Inductance; Packaging; Phase estimation; Phase noise; Pins; Plastics; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 1995. Proceedings., 45th

Conference_Location

Las Vegas, NV

Print_ISBN

0-7803-2736-5

Type

conf

DOI

10.1109/ECTC.1995.514407

Filename

514407