• DocumentCode
    2354648
  • Title

    On finding and modelling nested permutations in graphs

  • Author

    Shiran, Yehuda

  • Author_Institution
    Silvar-Lisco, Menlo Park, CA, USA
  • fYear
    1988
  • fDate
    7-9 Jun 1988
  • Firstpage
    1827
  • Abstract
    The problem of nested permutations originated in the area of VLSI layout verification. The author presents a way to find nested permutations automatically and to mark the permutations on the graph itself so that they are available for other applications. Designated pointers are added to the graph to show the permutable devices and the hierarchy of the permutations. The proposed approach is applied to NMOS gates
  • Keywords
    MOS integrated circuits; VLSI; circuit layout; graph theory; NMOS gates; VLSI layout verification; hierarchy; nested permutations in graphs; permutable devices; pointers; Circuit topology; Databases; Labeling; MOS devices; Network topology; Pins;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1988., IEEE International Symposium on
  • Conference_Location
    Espoo
  • Type

    conf

  • DOI
    10.1109/ISCAS.1988.15291
  • Filename
    15291
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2354648