DocumentCode :
2354674
Title :
Skipper: a microarchitecture for exploiting control-flow independence
Author :
Cher, Chen-Yong ; Vijaykumar, T.N.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear :
2001
fDate :
1-5 Dec. 2001
Firstpage :
4
Lastpage :
15
Abstract :
Although modern superscalar processors achieve, high branch prediction accuracy, certain branches either are inherently difficult to predict or incur destructive interference in prediction tables, causing significant performance loss due to mispredictions. We propose a novel microarchitecture, called Skipper, to handle such difficult branches by exploiting control-flow independence. Previous approaches to handling difficult branches, one way or another, amount to executing incorrect instructions, squandering cycles and resources such as the i-cache bandwidth. Skipper, altogether avoids incorrect instructions by skipping over, without even fetching, the control-flow dependent computation conditioned by a difficult branch. Instead, Skipper fetches and executes the control-flow independent instructions, which are past the point where the branch´s taken and not-taken paths reconverge, and which need to be executed irrespective of the branch outcome. Because Skipper executes the correct control-flow dependent instructions after the difficult branch is resolved, it conserves the valuable resources. Skipper is the first proposal to exploit control-flow independence by skipping over control-flow dependent computation in a superscalar pipeline. Skipper fetches the skipped control-flow dependent instructions after the post-reconvergent instructions, out of program order. We describe key mechanisms to implement Skipper without unduly complicating the pipeline despite out-of-order fetch. SPECint95 simulations show that Skipper performs 10% and 8% better than superscalar and the previously-proposed Polypath, respectively, when all three microarchitectures have equal i-cache bandwidth and hardware resources.
Keywords :
parallel architectures; performance evaluation; SPECint95 simulations; Skipper; control-flow dependent instructions; control-flow independence; control-flow independent instructions; i-cache bandwidth; microarchitecture; performance loss; superscalar pipeline; superscalar processors; Accuracy; Bandwidth; Computational modeling; Computer aided instruction; Interference; Microarchitecture; Out of order; Performance loss; Pipelines; Proposals;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microarchitecture, 2001. MICRO-34. Proceedings. 34th ACM/IEEE International Symposium on
ISSN :
1072-4451
Print_ISBN :
0-7965-1369-7
Type :
conf
DOI :
10.1109/MICRO.2001.991101
Filename :
991101
Link To Document :
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