Differential Delay Compensator -- A New Approach to Reduce Buffer Size in VCAT Enabled Next Generation SDH Networks

Next-generation SONET/SDH technologies namely, Generic Framing Procedure (GFP), Virtual Concatenation (VCAT) and Link Capacity Adjustment Scheme (LCAS) enable network operators to provide integrated data and voice services over their legacy SONET/SDH infrastructure to generate new revenue. VCAT is a inversing multiplexing technology used to break the GFP framed data payload such that it can be mapped into SDH frame. It groups arbitrary number of virtual containers to achieve the desired data rate. The number of virtual containers forms a group named virtual containers group (VCG). Individual member of VCG can traverse through any path to reach the destination and all VCs are combined at the destination as per the MFI (Multiframe Indicator) and Sequence Number written in the control packet of the SDH frame. As all the VCG members are routed independently, they do not reach the destination at the same time. These streams thus incur differential delay. Buffers are provided at the receiver to compensate differential delay and combine the streams for generating the data signal. More the differential delay more is the buffer requirement at the receiver. Differential delay/buffer size can be reduced by proper routing of the traffic. In the existing receiver circuits, all incoming streams are allotted fixed and equal buffer size, specifying maximum differential delay it can compensate. This results in large amount of buffer requirement and wastage of buffer as all the streams do not suffer same differential delay. To overcome this limitation, this paper proposes a novel scheme of allotting buffers dynamically to all the streams. To achieve this, differential delay between the streams is computed by extracting the MFI and then as per the delay, each stream is allotted buffer from a common buffer pool. The common buffer pool size is network architecture dependent. This scheme drastically reduces the buffer requirement at the receiver. For functional verification of the concep- t hardware circuit is designed. The circuit accepts three VC-3 streams, calculates the differential delay, allots buffers as per the delay and finally outputs synchronized streams compensating the differential delay.