DocumentCode
2354842
Title
Reducing power with dynamic critical path information
Author
Seng, John S. ; Tune, Eric S. ; Tullsen, Dean M.
Author_Institution
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
fYear
2001
fDate
1-5 Dec. 2001
Firstpage
114
Lastpage
123
Abstract
Recent research has shown that dynamic information regarding instruction criticality can be used to increase microprocessor performance. Critical path information can also be used in processors to achieve a better balance of power and performance. This paper uses the output of a dynamic critical path predictor to decrease the power consumption of key portions of the processor without incurring a corresponding decrease in performance. The optimizations include effective use of functional units with different power and latency characteristics and decreased issue logic power.
Keywords
microprocessor chips; performance evaluation; power consumption; dynamic critical path information; dynamic information; functional units; instruction criticality; issue logic power; latency characteristics; microprocessor performance; power characteristics; Circuits; Clocks; Computer science; Delay; Energy consumption; Logic devices; Microprocessors; Power engineering and energy; Process design; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Microarchitecture, 2001. MICRO-34. Proceedings. 34th ACM/IEEE International Symposium on
ISSN
1072-4451
Print_ISBN
0-7965-1369-7
Type
conf
DOI
10.1109/MICRO.2001.991110
Filename
991110
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