DocumentCode
2355027
Title
Catastrophic defects oriented testability analysis of a class AB amplifier
Author
Sachdev, Manoj
Author_Institution
Philips Res. Lab., Eindhoven, Netherlands
fYear
1993
fDate
27-29 Oct 1993
Firstpage
319
Lastpage
326
Abstract
Process defects have been recognized as one of the major contributors to the yield loss in CMOS integrated circuits. Any test philosophy without taking into consideration the probable processing defects is likely to compromise the quality of the tested devices. Owing to the specification oriented testing, analog devices frequently suffer from quality and reliability related issues. However, defect oriented testability analysis can be utilized to improve the quality of test methods and reduce the test costs. Furthermore, this analysis can provide inputs to the designer to improve the design robustness against the likely process defects. This methodology has been demonstrated with an example of a class AB amplifier
Keywords
CMOS analogue integrated circuits; CMOS integrated circuits; analog devices; class AB amplifier; defect oriented testability analysis; design robustness; probable processing defects; process defects; quality; reliability; simulation; specification oriented testing; test costs; yield loss; Analog circuits; Analog integrated circuits; Analytical models; CMOS process; CMOS technology; Circuit faults; Circuit testing; Costs; Laboratories; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on
Conference_Location
Venice
ISSN
1550-5774
Print_ISBN
0-8186-3502-9
Type
conf
DOI
10.1109/DFTVS.1993.595828
Filename
595828
Link To Document