Paradigm Cliff 2020 — The future of semi-conductor device and CMP technologies

We have so far discussed the red bricks and difficult changes regarding (1) Scaling, (2) Wafer transition and (3) 3D packages using Paradigm Shifts 45 and 20. Now is the time to discuss the Last Paradigm Shift 10 or Paradigm Cliff which means the real crisis. PS 10 nm: Transistor scaling will be positive up to 5 nm or less. However, interconnect scaling is delayed after 20 nm. The difficult challenge is to avoid electron scattering or to use different material except Cu or to adopt another integration methods. PS 10 cm: 450 mm wafer seems to be the final wafer size transition. So, we need the idea after 450. The unique idea is discussed herein. PS 10 um: If the wafer thickness is 100 um with TSV hole diameter 10 um, the aspect ratio is 10. However, if the wafer thickness becomes below 10 um, the aspect ratio will be below 1. Plating comes very easy. The question is how thin wafer is accepted. Paradigm Cliff: All development seems to be standing on Paradigm Cliff. Let´s discuss what will happen after 10 nm. CMP technology support should be also discussed.