Improving defectivity for III-V CMP processes for <10 nm technology nodes

III-V high mobility channel materials are being considered for advanced devices beyond the 10 nm technology node. For pMOS devices, Ge and SiGe have already been shown to be viable candidates [1,2] while for nMOS devices our focus lies on III-V materials such as InP and InGaAs. For the integration of III-V channel materials, several approaches are being explored: the aspect ratio trapping (ART) method and hetero-epitaxy of III-V compound semiconductors on blanket Si using strain-relaxed buffer layers. This paper focuses on reducing the defectivity of the III-V layers during CMP steps needed for either approach. We show that the use of an improved pad/slurry combination can significantly reduce the CMP-induced damage to the InP fins in the ART approach and can achieve a post-CMP roughness r.m.s. of InGaAs SRB layers of ~0.7 nm.