W CMP for C14nm and Beyond: Barrier selective approach

Beyond C14nm, better W CMP performances are required due to new CMOS integration constraints such as contact density increase, wide W feature introduction or low oxide loss for any polishing steps related to gate building. In order to address these new requirements, this paper propose an approach similar to Cu damascene CMP, using three consecutive polishing steps respectively for planarization, selective stop on Ti/TiN barrier and barrier removal. This study discuss advantages and limitations of this approach and points out process improvement obtained among which lower oxide erosion, tunable W recess, better oxide WIWNU and minimized oxide loss.