Practical usage of simulation technology in CMP process development

In CMP process development for mass production of semiconductor devices, not only good planarity and uniformity but also compatibility with productivity such as defect reduction and cost performance is important. Exploiting the power of simulation technology is effective in such development, since it enables prediction of possible issues in advance so the total optimization of process integration and wiring design could be realized. In this presentation, two effective applications of simulations for CMP process development are addressed. First, an original Cu-CMP process model was developed on a commercially available CMP simulation tool of Mentor Graphics. This enables hotspot extraction from new designed product data [1]. Next, a simulation using finite element method (FEM) revealed that low-k delamination was caused by the local pressure concentration on the wafer. This issue was resolved by adopting a novel concept polishing pad which decreases the pressure concentration [2].