Low-frequency testing of through silicon vias for defect diagnosis in three-dimensional integration circuit stacking technology

In order to qualify through silicon via (TSV) structures during manufacturing effectively and efficiently, two low-frequency testing methods were proposed here for electrical property and defect diagnosis of TSV samples. The first method (Method I) based on four-point probe test was adopted to measure via resistance and contact resistance, while the second method (Method II) based on two-point probe test was used to verify insulation integrity of TSVs. We adopted Simulated Method of Moments to illustrate the testing principles, carried out self-designed tests, and prepared samples on an industrial TSV packaging line as experimental validation. The effectiveness of the tests methods on four common types of defects were demonstrated by the simulation and test data analysis. The test methods proposed in this paper introduce a simple and low-cost solution for improving production efficiency in 3D integration circuit stacking technology, and they are being integrated into practical techniques for the industrial TSV packaging line.