Silicon nitride stop layer in back-end-of-line planarization for wafer bonding application

We introduce an approach that combines a 3” InP-DHBT transferred-substrate process with a SiGe-BiCMOS process. First, silicon and InP wafers are processed separately in different fabs. The silicon wafer runs through the complete 0.25 μm BiCMOS production process with five metal layers aluminum/tungsten back-end-of-line using silicon dioxide as dielectric. The processing was adapted for the following wafer bond process by planarization of the topmost metal level. This process flow was improved by using a SiN CMP stop layer on top of the metal layer stack, comparable to trench fill planarization. In that way a low surface topography was reached, this guarantees proper bonding results. Different mm-wave circuits operating at frequencies up to 246 GHz were produced to demonstrate the capability of the process flow.