Yield analysis of compiler-based arrays of embedded SRAMs

Author

Wang, X. ; Ottavi, M. ; Lombardi, F.

Author_Institution

Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA

fYear

2003

fDate

3-5 Nov. 2003

Firstpage

3

Lastpage

10

Abstract

This paper presents a detailed analysis of the yield of embedded static random access memories (eSRAM) which are generated using a compiler. Defect and fault analysis inclusive of industrial data are presented for these chips by taking into account the design constructs (referred to as kernels) and the physical properties of the layout. The new tool CAYA (Compiler-based Array Yield Analysis) is based on a characterization of the design process which accounts for fault types and the relation between functional and structural faults; a novel empirical model is proposed to facilitate the yield calculation. Industrial data is provided for the analysis of various configurations with different structures and redundancy. The effectiveness and accuracy as provided by CAYA are assessed with respect to industrial designs.

Keywords

SRAM chips; circuit CAD; circuit analysis computing; circuit layout CAD; failure analysis; fault diagnosis; fault simulation; integrated circuit design; integrated circuit modelling; integrated circuit reliability; integrated circuit yield; software tools; CAYA tool; Compiler-based Array Yield Analysis tool; IC design techniques; compiler-based arrays; defect analysis; design constructs; design process characterization; embedded SRAM; embedded static random access memories; empirical yield calculation model; fault analysis; fault types; functional faults; industrial data; industrial designs; kernels; layout physical properties; redundancy; structural faults; yield analysis; Application specific integrated circuits; Circuit faults; Driver circuits; Industrial relations; Integrated circuit yield; Kernel; Manufacturing industries; Monitoring; Random access memory; Redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-2042-1

Type

conf

DOI

10.1109/DFTVS.2003.1250089

Filename

1250089