• DocumentCode
    2356126
  • Title

    Simplified Multi-Level Quasi-Cyclic LDPC Codes for Low-Complexity Encoders

  • Author

    Mahdi, Ahmed ; Paliouras, Vassilis

  • Author_Institution
    Electr. & Comput. Eng. Dept., Univ. of Patras, Patras, Greece
  • fYear
    2012
  • fDate
    17-19 Oct. 2012
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    In this paper we propose a parity check matrix construction technique that simplifies the hardware encoders for Multi-Level-Quasi-Cyclic (ML-QC) LDPC codes. The proposed construction method is based on semi-random - ML-QC extension and appropriately selects shifting factors to reduce the density of the inverted matrix used in several encoding algorithms. The construction method derives low-complexity encoders with minimal degradation of error-correction performance, observable at low BER only. Furthermore a VLSI encoding architecture based on the suggested parity-check matrix (PCM) is also introduced. Experimental results show that the complexity of the proposed encoders depends on the density of the binary base matrix. A comparison with random QC codes reveals substantial complexity reduction without performance degradation for cases of practical interest. In fact a hardware complexity reduction by a factor of 7.5 is achieved, combined with the acceleration of the encoder, for certain cases.
  • Keywords
    VLSI; binary codes; cyclic codes; matrix inversion; parity check codes; VLSI encoding architecture; binary base matrix; construction method; encoding algorithm; error-correction performance; hardware complexity reduction; hardware encoder; inverted matrix; low-complexity encoder; multilevel quasi-cyclic LDPC code; multilevel-quasi-cyclic LDPC code; parity check matrix construction; parity-check matrix; shifting factor; Bit error rate; Complexity theory; Decoding; Encoding; Hardware; Parity check codes; Phase change materials; LDPC encoding; ML - quasi-cyclic LDPC; hardware architecture; matrix inversion;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Systems (SiPS), 2012 IEEE Workshop on
  • Conference_Location
    Quebec City, QC
  • ISSN
    2162-3562
  • Print_ISBN
    978-1-4673-2986-6
  • Type

    conf

  • DOI
    10.1109/SiPS.2012.21
  • Filename
    6363175