P2P-6 Trench-Isolated CMUT Arrays with a Supporting Frame

We present a trench-isolated CMUT process with a supporting mesh frame for a fully populated 2D array. In this process, the CMUT array is built on a silicon-on-insulator (SOI) wafer. Electrical interconnections to array elements are provided through the highly conductive silicon substrate. Neighboring array elements are separated from one another by trenches on both the device layer and the bulk silicon. A mechanically supporting frame is designed as a mesh structure between the silicon pillars providing electrical connections to the individual elements. Like the frameless trench isolation process, the framed trench isolation is compatible with both wafer-bonded and surface-micromachined CMUTs. In addition, this process eliminates the need for attaching the device wafer to a carrier wafer for the required mechanical support during the deep trench etching and flip-chip bonding steps, which presents difficulties during the release of the carrier wafer