DocumentCode
2356208
Title
Level-hybrid optoelectronic TESH interconnection network
Author
Jain, Vijay ; Chapman, Glenn
Author_Institution
Univ. of South Florida, Tampa, FL, USA
fYear
2003
fDate
3-5 Nov. 2003
Firstpage
45
Lastpage
52
Abstract
This paper discusses a hybrid optoelectronic scheme for a new interconnection network "Tori connected meshes (TESH)". The major features of TESH are the following: it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion up to a million processors or devices, it permits efficient VLSI/ULSI realization, it is designed to make use of redundancy for defect circumvention, and it appears to be well suited for 3D stacked implementation. Here, we discuss a novel extension to these capabilities through the provision of optical interconnections at the highest level, while keeping the lower levels electronic through metal wires. The advantages of the resulting architecture, dubbed level-hybrid optoelectronic TESH, are the elimination of bottlenecks which typically occur at the highest level due to the aggregation of traffic, and the reduction of cost by using traditional wire channels at the lower levels - where optical links are deemed unnecessary.
Keywords
ULSI; VLSI; hierarchical systems; integrated circuit interconnections; integrated optoelectronics; multiprocessor interconnection networks; network topology; optical interconnections; redundancy; 3D stacked implementation; TESH; Tori connected meshes; ULSI realization; VLSI realization; computation locality; defect circumvention; electronic lower level interconnections; hierarchical scheme; hybrid optoelectronic scheme; interconnection network; level-hybrid optoelectronic TESH interconnection network; metal wires; optical interconnections; optical links; processors; redundancy; traffic aggregation; wire channels; Costs; Multiprocessing systems; Multiprocessor interconnection networks; Optical devices; Optical fiber communication; Optical interconnections; Redundancy; Silicon; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on
ISSN
1550-5774
Print_ISBN
0-7695-2042-1
Type
conf
DOI
10.1109/DFTVS.2003.1250094
Filename
1250094
Link To Document