CodSim - a combined delay fault simulator

Author

Qiu, Wangqi ; Lu, Xiang ; Li, Zhuo ; Walker, F. M H ; Shi, Weiping

Author_Institution

Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA

fYear

2003

fDate

3-5 Nov. 2003

Firstpage

79

Lastpage

86

Abstract

Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this problem a combined delay fault (CDF) model has been developed, which models delay faults caused by the combination of spot defects, parametric process variation, and capacitive coupling. The spot defects are modeled as both resistive opens and shorts. The CDF model has been implemented in the CodSim delay fault simulator which gives more realistic delay fault coverage. The fault coverage of traditional test sets has been evaluated on the ISCAS85 circuits.

Keywords

circuit analysis computing; circuit simulation; delays; failure analysis; fault simulation; integrated circuit modelling; integrated circuit testing; CDF model; CodSim combined delay fault simulator; ISCAS85 circuits; capacitive coupling; combined delay fault model; delay defect behavior subsets; delay fault coverage; delay fault test; delayfault modets; parametric process variation; resistive opens; shorts; spot defects; test sets; Circuit faults; Circuit noise; Circuit simulation; Circuit testing; Computational modeling; Computer science; Coupling circuits; Delay; Electrical fault detection; Hazards;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-2042-1

Type

conf

DOI

10.1109/DFTVS.2003.1250098

Filename

1250098